Biographical data

· Born in Turin, Italy on October 6, 1960.

· Italian citizen.

· Married with two children.

Higher education

· Graduation in Electronic Engineering “magna cum laude”: on December 17, 1985 from Politecnico di Torino, defending the final project work “Use of CONLAN in the definition of hardware description languages”

· PhD in Computer Engineering: from November 1985 to October 1988, graduation on September 12^th, 1989 defending the thesis “Formal verification of digital design correctness and of design rules”.

Academic career

· Researcher at Dipartimento di Automatica e Informatica of Politecnico di Torino from November 1990 to October 1992.

· Associate Professor at Dipartimento di Automatica e Informatica of Politecnico di Torino from November 1992 to October 1994.

· Full Professor at Dipartimento di Matematica e Informatica of Università di Udine from November 1994 to October 1997.

· Full Professor at Dipartimento di Automatica e Informatica of Politecnico di Torino from November 1997.

Areas of scientific activity

· Systems and tools for CAD of VLSI

· Testing and simulation of digital devices

· Hardware description languages

· Formal verification of hardware design correctness

· Application of AI techniques to electronic CAD, CAT, CAR, and CAE.

Teaching duties

· Digital design

· Algorithms and advanced programming

· Computer architecture

· Fundamentals of Computer Engineering

Academic roles

· In charge of Socrates student exchanges for the School of Information Technologies (from 1996)

· Member of the International Relations Board of Politecnico di Torino

· Currently Deputy Dean of the School of Information Technologies.

Publications

· Author or co-author of:

· 20 papers on internationally refereed journals

· 65 papers at internationally refereed conferences.

· Co-editor of the Advanced Workshop On Correct Hardware Design Methodologies, papers published by North Holland, Amsterdam, 1991

· Member of the following program committees:

· CHARME-93: Advanced Research Workshop on Correct Hardware Methodologies, Arles (F), April 1993, Springer Verlag, Berlin (Germania), nella collana Lecture Notes in Computer Science n. 683

· ICCD: IEEE International Conference on Computer Design (1994-96)

· EDAC: IEEE European Design Automation Conference (1995-97)

· EuroDAC: IEEE European DAC (1996-2002)

· CHARME-97: Advanced Research Workshop on Correct Hardware Methodologies, Montreal (Canada), October 1997, Chapman & Hill

· CHARME-99: Advanced Research Workshop on Correct Hardware Methodologies, Karlsruhe (Germany), October 1999

· Invited Speaker to several international conferences

· Reviewer for more than 30 papers submitted to international journals and conferences.

Paolo CAMURATI: publication list

1986

[Jou/86-1]

G.Cabodi, P.Camurati, P.Prinetto, M.Sonza Reorda:

“C_TPDL*: adapting TPDL* to concurrent simulation,'“

Microprocessing and Microprogramming, The Euromicro Journal, Vol. 18, n. 1-5, December 1986, pp. 39-46

[Jou/86-2]

G.Cabodi, P.Camurati, P.Prinetto:

“An extension to Base ConLan in the temporal domain,”

Microprocessing and Microprogramming, The Euromicro Journal, Vol. 18, n. 1-5, December 1986, pp. 559-566

1988

[Jou/88-1]

P.Camurati, P.Prinetto:

“Formal verification of hardware correctness: introduction and survey of current research,”

IEEE Computer, Vol. 21, n. 7, July 1988, pp. 8-19, also in “Formal Verification of Hardware Design”, M. Yoeli editor, IEEE Computer Society Press Tutorial, 1990, pp. 5-16

[Jou/88-2]

P.Camurati, P.Gianoglio, R.Gianoglio, P.Prinetto:

“ESTA: an Expert System for Testability Automation,”

IEEE Transactions on Computer Aided Design, Vol. 7, n. 11, November 1988, pp. 1172-1180

1989

[Jou/89-1]

P.Camurati, P.Prinetto:

“Verification of hardware design,”

Datapro Management of EDP systems, McGraw-Hill, Vol. 14, n. 1, January 1989, pp. E50-100-801-814

[Jou/89-2]

P.Camurati, M.Mezzalama, P.Prinetto:

“The use of knowledge-based systems as an aid to CAR,”

Microprocessors and Microsystems, Vol. 13, No. 7, September 1989, pp. 457-461

[Jou/89-3]

P.Camurati, M.Fourman, C.Pixley, P.Prinetto, S-K.Chin, H.Takahara:

“Formal verification: is it practical for real-world design?,”

IEEE Design & Test of Computers, December 1989, pp. 50-58 (D&T roundtable)

[Jou/89-4]

G.Cabodi, P.Camurati, P.Prinetto, M.Sonza Reorda:

“Expressing logical and temporal conditions in simulation environments: TPDL*,”

Microprocessing and Microprogramming, The Euromicro Journal, Vol. 26, 1989,

pp. 241-252

[Jou/89-5]

P.Camurati, T. Margaria, P.Prinetto:

“Systolic array description in F²,”

Microprocessing and Microprogramming, The Euromicro Journal, Vol. 27, 1989,

pp. 171-178

1990

[Jou/90-1]

P.Camurati, P.Prinetto:

“Formal techniques for hardware correctness verification: an introduction,”

“Progress in computer-aided VLSI design,” Volume 2: Techniques, G. Zobrist editor, Ablex Publishing Corporation, 1990, pp. 1-22

[Jou/90-2]

P.Camurati, P.Prinetto:

“Formal techniques for hardware correctness verification: current research activities,”

“Progress in computer-aided VLSI design,” Volume 2: Techniques, G. Zobrist editor, Ablex Publishing Corporation, 1990, pp. 23-42

[Jou/90-3]

P.Camurati, P.Prinetto, M.Sonza Reorda:

“Exact probabilistic testability measures for multi-output circuits,”

JETTA: Journal of Electronic Testing: Theory and Applications, Vol. 1, n. 3, 1990, pp. 229-235

[Jou/90-4]

P.Camurati, T.Margaria, P.Prinetto:

“The OTTER environment for resolution-based proof of hardware correctness,”

Microprocessing and Microprogramming, The Euromicro Journal, Vol. 30, n. 1-5, August 1990, pp. 413-419

[Jou/90-5]

P.Camurati, A.Lioy, P.Prinetto, M.Sonza Reorda:

“Assessing diagnostic capabilities of test pattern sets,”

Microprocessing and Microprogramming, The Euromicro Journal, Vol. 30, n. 1-5, August 1990, pp. 421-428

[Jou/90-6]

D.Borrione, P.Camurati, JL.Paillet, P.Prinetto:

“Functional approaches applied to Microprogrammed Architectures,”

International Journal of Computer Aided VLSI Design, Vol. 2, N. 3, 1990, pp. 339-358

1991

[Jou/91-1]

G.Cabodi, P.Camurati, P.Prinetto, M.Sonza Reorda:

“TPDL*: Extended Temporal Profile Description Language,”

Software - Practice and Experience, Vol. 21(4), April 1991, pp. 355-374

1993

[Jou/93-1]

G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda:

“An Approach to Sequential Circuit Diagnosis based on Formal Verification Techniques”

JETTA: Journal of Electronic Testing: Theory and Applications, Vol. 4, n. 1, February 1993, pp. 11-17

1995

[Jou/95-1]

P. Camurati, P. Prinetto, M. Sonza Reorda, S. Barbagallo, A. Burri, D. Medina:

“An industrial experience in the built-in self test of embedded RAMs,”

IEEE Design & Test of Computers, vol. 12, n. 3, Fall 1995, pp. 86-95

1997

[Jou/97-1]

G. Cabodi, P. Camurati:

“Symbolic FSM Traversal based on the Transition Relation,”

IEEE Transactions on Computer Aided Design, vol. 16, n. 5, May 1997, pp. 448-457

[Jou/97-2]

G. Cabodi, P. Camurati, S. Quer:

“Auxiliary Variables for BDD-based Representation and Manipulation of Boolean Functions,”

to appear on ACM Transactions on Design Automation of Electronic Systems

1998

[Jou/98-1]

G. Cabodi, P. Camurati, S. Quer:

“Memory optimization in Function and Set Manipulation with BDDs,”

Software Practice & Experience, vol. 28(1), January 1998, pp. 99-120

[Jou/98-2]

G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda:

“The General Product Machine: a New Model for Symbolic FSM Traversal,”

International Journal on Formal Methods in System Design, Kluwer Academic Publishers, 12, pp. 267-289 (1998)

[Jou/98-3]

G. Cabodi, P. Camurati, S. Quer:

“Implicit Manipulation of Equivalence Classes for Large Finite State Machines,”

IEE Proceedings Comput. Digit. Tech., Vol. 145, No. 6, November 1998, pp. 395-402

1999

[Jou/99-1]

G. Cabodi, P. Camurati, S. Quer:

“Improving the Efficiency of BDD-based operators through Partitioning”

IEEE Transactions on Computer Aided Design, vol. 18, n. 5, May 1999, pp. 545-556

2000

[Jou/00-1]

G. Cabodi, P. Camurati, S. Quer:

“Symbolic Forward/Backward Traversals of Large Finite State Machines,”

Journal of Systems Architecture 46(2000), pp. 1137-1158

[Jou/00-2]

G. Cabodi, P. Camurati, C. Passerone, S. Quer:

“Exploiting Timed Transition Relations in Sequential Cycle-Based Simulation of Embedded Systems”

IEE Proceedings – Computers and Digital Techniques, Vol. 147, No. 5, September 2000, pp. 305-312

[Jou/00-3]

G. Cabodi, P. Camurati, S. Quer:

“Improving symbolic reachability analysis by means of activity profiles”

IEEE Transactions on Computer Aided Design, vol. 19, n. 9, September 2000, pp. 1065-1075

[Jou/00-4]

S. Quer, G. Cabodi, P. Camurati, L. Lavagno, E. M. Sentovich, R. K. Brayton:

“Verification of Similar FSMs by mixing Incremental Re-encoding Reachability Analysis and Combinational Checks”

Formal Methods In System Design, 17, pp. 107-134, 2000, Kluwer Academic Publishers

2001

[Jou/01-1]

G. Cabodi, P. Camurati, S. Quer:

“Reachability Analysis of Large Circuits Using Disjunctive Partitioning and Partial Iterative Squaring,”

Journal of Systems Architecture, 47 (2001), pp. 163-179

Conferences

1985

[Con/85-1]

G.Cabodi, P.Camurati, P.Prinetto:

“Applications of Artificial Intelligence techniques to design for testability verification,”

MIMI'85: ISMM Mini And Microcomputers And Their Applications, Sant Feliu de Guixols (Spain), June 1985, pp. 7-10

[Con/85-2]

G.Cabodi, P.Camurati, P.Prinetto:

“Interpretation of a CAD system Data Base as a Semantic Network,”

MIMI'85: ISMM Mini And Microcomputers And Their Applications, Sant Feliu de Guixols (Spain), June 1985, pp. 11-14

[Con/85-3]

G.Cabodi, P.Camurati, G.Crosetti, P.Prinetto:

“Experiences in CONLAN based formal verification of HDL's,”

CHDL'85: IFIP 7th Int. Symposium on Computer Hardware Description Languages and their Applications, Tokyo (Japan), August 1985, pp. 452-465

[Con/85-4]

G.Cabodi, P.Camurati, P.Prinetto:

“TPDL*: a language to describe temporal conditions from behaviour to electric level,”

EUROMICRO'85: Microcomputers, usage and design: 11th Euromicro symposium on

Microprocessing and Microprogramming, Brussels (Belgium), September 1985, pp. 487-495

[Con/85-5]

G.Cabodi, P.Camurati, P.Prinetto:

“The use of CONLAN in formal syntactic and semantic verification of Hardware Description Languages,”

EUROMICRO'85: Microcomputers, usage and design: 11th Euromicro symposium on

Microprocessing and Microprogramming, Brussels (Belgium), September 1985, pp. 497-506

1986

[Con/86-1]

G.Cabodi, P.Camurati, P.Prinetto:

“The use of Prolog for executable specification and verification of easily testable designs,”

FTCS'16: IEEE 16th Annual International Symposium on Fault Tolerant Computing Systems, Vienna, Austria, July 1986, pp. 390-395

[Con/86-2]

G.Cabodi, P.Camurati, P.Prinetto:

“Experiences in Prolog based DFT rule checking,”

FJCC'86: IEEE Fall Joint Computer Conference, Dallas Texas (USA), November 1986, pp. 909-914

1987

[Con/87-1]

P.Camurati, P.Prinetto:

“Formal verification techniques,”

CHDL'87: IFIP 8th Int. Symposium on Computer Hardware Description Languages and their Applications, Amsterdam (The Netherlands), April 1987, pp. 225-247 (Invited tutorial)

[Con/87-2]

P.Camurati, M.Mezzalama, P.Prinetto:

“Improving Diagnostic capabilities of ATEs via AI techniques,”

in “Fault Detection & Reliability: knowledge based & other approaches”, M.G. Singh, K.S. Hindi, and S. Tzafestas editors, International Series on Systems and Control, Vol. 9, Pergamon Press, 1987, pp. 51-58

[Con/87-3]

G.Cabodi, P.Camurati, P.Prinetto:

“Event-driven functional evaluation of temporal conditions in concurrent mixed-mode simulation,”

CompEuro'87: IEEE Conference on VLSI and Computers, Hamburg (FRG), May 1987, pp. 219-223

[Con/87-4]

P.Camurati, P.Prinetto:

“Knowledge Based Systems for CAD, CAT, and CAR: reality or utopia?,”

CompEuro'87: IEEE Conference on VLSI and Computers, Hamburg (FRG), May 1987, pp. 444-450 (Invited presentation)

[Con/87-5]

P.Camurati, P.Prinetto:

“ProTest: a Design for Testability oriented Prolog Hardware Description Language,”

ICCD'87: IEEE International Conference on Computer Design: VLSI in computers & processors, Port Chester (NY), October 1987, pp. 297-300

1988

[Con/88-1]

GP.Cabodi, P.Camurati, P.Prinetto, M.Sonza Reorda:

“An abstract model supporting run-time evaluation of temporal expressions”

IASTED Applied Informatics, Grindelwald (Switzerland), February 1988, pp. 5-8

[Con/88-2]

G.Battistoni, P.Camurati, P.Prinetto, M.Sonza Reorda:

“IWDL: an Input Waveform Description Language”

IASTED Applied Informatics, Grindelwald (Switzerland), February 1988, pp. 194-197

[Con/88-3]

P.Camurati, M.Mezzalama, P.Prinetto:

“Application of AI techniques in CAR environments,”

IFAC DIS'88: distributed intelligent systems methods and applications, Varna (Bulgaria), June 1988, pp. 286-290

[Con/88-4]

P.Camurati, T.Margaria, P.Prinetto:

“VLSI functional descriptions in F²,”

``Design Methodologies for VLSI and Computer Architecture'', D.A. Edwards

Editor, Elsevier Science Publishers, 1989, pp. 169-181

[Con/88-5]

P.Camurati, P.Prinetto, M.Sonza Reorda:

“Random Testability Analysis: comparing and evaluating existing approaches,”

ICCD'88: IEEE International Conference on Computer Design: VLSI in Computers & Processors, Rye Brook, NY (USA), October 1988, pp. 70-73

[Con/88-6]

D.Borrione, P.Camurati, J.L.Paillet, P.Prinetto:

“A functional approach to formal hardware verification: the MTI experience,”

ICCD'88: IEEE International Conference on Computer Design: VLSI in Computers & Processors, Rye Brook, NY (USA), October 1988, pp. 592-595

[Con/88-7]

P.Camurati, M.Mezzalama, P.Prinetto, M.Sonza Reorda:

“L'uso di Sistemi Esperti nel CAD, CAT e CAR elettronico,”

CAA'88 Convegno AICA-ANIPLA “Informatica ed automatica di fabbrica”, Turin (Italy), November 1988, pp. 315-326

1989

[Con/89-1]

P.Camurati, T. Margaria, P.Prinetto:

“The Use of F² in Functional Descriptions of VLSI,”

7th IASTED Applied Informatics, Grindelwald (Switzerland), February 1989, pp. 219-222

[Con/89-2]

G.Cabodi, P.Camurati, P.Prinetto, M.Sonza Reorda:

“Testability Measures with Concurrent Good Simulation,”

ETC'89: IEEE 1st European Test Conference, Paris (France), April 1989, pp. 144-149

[Con/89-3]

D.Borrione, P.Camurati, J.L.Paillet, P.Prinetto:

“Formal verification of microprogrammed architectures,”

International Conference on CAD & CG, Beijing (China), August 1989, pp. 562-567

[Con/89-4]

P.Camurati, P.Prinetto, M.Sonza Reorda:

“Probabilistic Testability Analysis,”

International Conference on CAD & CG, Beijing (China), August 1989, pp. 640-645

[Con/89-5]

P.Camurati, P.Prinetto, M.Sonza Reorda:

“Exact probabilistic testability measures for multi-output circuits,”

in “Robotic Systems amd AMT”, G. Halevi, R. Weill, and I. Yudilevich Editors, Elsevier Science Publishers, 1990, pp. 293-302

1990

[Con/90-1]

P.Camurati, A.Lioy, P.Prinetto, M.Sonza Reorda:

“Diagnosis Oriented Test Pattern Generation,”

EDAC'90: IEEE European Design Automation Conference, Glasgow (UK), March 1990, pp. 470-474

[Con/90-2]

P.Camurati, D.Medina. P.Prinetto, M.Sonza Reorda:

“A new algorithm for diagnosis-oriented Automatic Test Pattern Generation,”

IEEE EUROASIC'90, May 1990, Paris (France), pp. 332-336

[Con/90-3]

P.Camurati, M.Gilli, P.Prinetto, M.Sonza Reorda:

“Model Checking and Graph Theory in sequential ATPG,”

Workshop on Computer-Aided Verification, June 1990, Rutgers, NJ (USA), AMS/DIMACS Series in Discrete Mathematics and Theoretical Computer Science, Vol. 3, 1991, pp. 505-517

[Con/90-4]

P.Camurati, D.Medina. P.Prinetto, M.Sonza Reorda:

“A diagnostic test pattern generation algorithm,”

ITC'90: IEEE International Test Conference, September 1990, Washington, DC (USA), pp. 52-58

[Con/90-5]

P. Camurati, T. Margaria, P. Prinetto:

“Use of the OTTER theorem prover for the formal verification of hardware,”

Workshop on Designing Correct Circuits, September 1990, Oxford (UK), “Workshops in Computing”, G. Jones, M. Sheeran Eds., Springer Verlag, pp. 253-270

1991

[Con/91-1]

P. Camurati, T. Margaria, P. Prinetto:

“Resolution-oriented correctness proofs of synchronous circuits,”

EDAC'91: IEEE European Design Automation Conference, Amsterdam (The Netherlands), February 1991, pp. 11-15

[Con/91-2]

P. Camurati, M. Gilli, P. Prinetto, M. Sonza Reorda:

“Proving Finite State Machines correct with an automaton-based method,”

GLSV'91: IEEE First Great Lakes Symposium on VLSI, Kalamazoo, MI (USA), March 1991, pp. 255-258

[Con/91-3]

P. Camurati, M. Gilli, A.R. Meo, P. Prinetto, M. Sonza Reorda:

“Comparing ATPGs for synchronous sequential circuits,”

CompEuro'91: IEEE Conference on VLSI and Computers, Bologna (Italy), May 1991, pp. 224-228

[Con/91-4]

S. Barbagallo, A. Burri, D. Medina, P. Camurati, P. Prinetto, M. Sonza Reorda:

“An experimental comparison of different approaches to ROM BIST,”

CompEuro'91: IEEE Conference on VLSI and Computers, Bologna (Italy), May 1991, pp. 567-571

[Con/91-5]

P. Camurati, T. Margaria, P. Prinetto:

“Formal verification of design correctness of sequential circuits based on theorem provers,”

CompEuro'91: IEEE Conference on VLSI and Computers, Bologna (Italy), May 1991,

pp. 322-326

[Con/91-6]

P. Camurati, P. Prinetto:

“Striving toward correct FSMs: advances in design, formal verification, testing, and diagnosis,”

CompEuro'91: IEEE Conference on VLSI and Computers, Bologna (Italy), May 1991,

pp. 310-316 (Invited presentation)

[Con/91-7]

P. Camurati, M. Gilli, P. Prinetto, M. Sonza Reorda:

“The Product Machine and Implicit Enumeration to prove FSMs correct,”

Workshop On Correct Hardware Design Methodologies, Turin (Italy), June 1991, P. Prinetto, P. Camurati editors, North Holland, Amsterdam (The Netherlands), pp. 51-62

[Con/91-8]

P. Camurati, P. Prinetto:

“Design For Verifiability and Design For Testability: limiting designers' freedom to achieve what?,”

Workshop On Correct Hardware Design Methodologies, Turin (Italy), June 1991, P. Prinetto, P. Camurati editors, North Holland, Amsterdam (The Netherlands), pp. 295-309

1992

[Con/92-1]

P. Camurati, M. Rebaudengo, P. Prinetto, M. Sonza Reorda:

“Efficient verification of sequential circuits on a parallel system,”

EDAC'92: the European Conference on Design Automation, Brussels, (Belgium), March 1992, pp. 64-68

[Con/92-2]

P. Camurati, M. Rebaudengo, P. Prinetto, M. Sonza Reorda:

“Centralized vs. distributed implementation of FSM equivalence verification on a parallel system,”

EWPC'92: European Workshops on Parallel Computing, “Parallel Computing: from theory to sound practice”, W. Joosen and E. Milgrom, Eds., IOS Press, Barcelona (Spain), March 1992, pp. 554-557

[Con/92-3]

P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda:

“A simulation-based approach to test pattern generation for synchronous circuits,”

VTS'92: 10th IEEE VLSI Test Symposium, Atlantic City, NJ (USA), April 1992, pp. 263-267

[Con/92-4]

P. Camurati, M. Rebaudengo, P. Prinetto, M. Sonza Reorda:

“Improved techniques for multiple stuck-at fault analysis using single stuck-at fault test sets,”

ISCAS'92: IEEE International Symposium On Circuits and Systems, San Diego, CA (USA), May 1992, Vol. 1, pp. 383-386

[Con/92-5]

G. Cabodi, P. Camurati, F. Corno, S. Gai, P. Prinetto, M. Sonza Reorda:

“A new model for improving symbolic Product Machine traversal,”

DAC-29: 29th ACM/IEEE Design Automation Conference, Anaheim, CA (USA), June 1992, pp. 614-619

[Con/92-6]

G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda:

“Cross-fertilizing FSM verification techniques and sequential diagnosis,”

IEEE EURO-DAC'92, Hamburg (Germany), September 1992, pp. 306-311

[Con/92-7]

G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda:

“Sequential circuit diagnosis based on formal verification techniques,”

ITC'92: IEEE International Test Conference, Baltimore, MD (USA), September 1992, pp. 187-196

[Con/92-8]

P. Camurati, P. Prinetto, M. Rebaudengo, M. Sonza Reorda:

“Verifica di circuiti sequenziali su un sistema parallelo,”

AICA'92: 29^o Congresso Nazionale AICA, Turin (Italy), October 1992, pp. 115-124

[Con/92-9]

G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda:

Attraversamento simbolico di macchine a stati finiti per verifica, sintesi e collaudo,” AICA'92: 29^o Congresso Nazionale AICA, Turin (Italy), October 1992, pp. 133-145

[Con/92-10]

G. Cabodi, P. Camurati, F. Corno, P. Prinetto, M. Sonza Reorda:

“Tecniche di diagnosi per circuiti sequenziali,”

AICA'92: 29^o Congresso Nazionale AICA, Turin (Italy), October 1992, pp. 737-748

1993

[Con/93-1]

P. Camurati, F. Corno, P. Prinetto:

“System-level fault modeling and test pattern generation with Process Algebras,”

ETC'93: IEEE European Test Conference, Rotterdam (The Netherlands), April 1993, pp. 47-56

[Con/93-2]

P. Camurati, F. Corno, P. Prinetto:

“Exploiting symbolic traversal techniques for efficient Process Algebra Manipulation,”

CHDL'93: IFIP Conference on Hardware Description Languages and their Applications, Ottawa (Canada), April 1993, pp. 21-34

[Con/93-3]

G. Cabodi, P. Camurati:

“Advancements in Symbolic Traversal Techniques, “

IFIP WG 10.2 Advanced Research Working Conference CHARME'93, Arles (France), May 1993, G.J. Milne and L. Pierre editors, Lecture Notes in Computer Science 683, Springer Verlag, Berlin (Germany), pp. 155-166

[Con/93-4]

P. Camurati, F. Corno, P. Prinetto:

“A methodology for system-level design for verifiability,”

[Con/93-5]

P. Camurati, F. Corno, P. Prinetto:

“An efficient tool for system-level verification of behaviors and temporal properties,”

IEEE EURO-DAC'93, Hamburg (Germany), September 1993, pp. 124-129

[Con/93-6]

G. Cabodi, P. Camurati:

“Exploiting cofactoring for efficient FSM symbolic traversal based on the Transition Relation,”

ICCD'93: IEEE International Conference on Computer Design, Cambridge, MA (USA), October 1993, pp. 299-303

[Con/93-7]

G. Cabodi, P. Camurati, S. Quer:

“Boolean Function Decomposition in Symbolic FSM Traversal,”

ICVC'93: IEEE 3rd International Conference on VLSI and CAD, Taejon (Korea), November 1993, pp. 265-268

[Con/93-8]

P. Camurati, F. Corno, P. Prinetto, C. Bayol, B. Soulas:

“A Verifiable Design Methodology at System-Level,”

ICVC'93: IEEE 3rd International Conference on VLSI and CAD, Taejon (Korea), November 1993, November 1993, pp. 364-367

1994

[Con/94-1]

P. Camurati, F. Corno, P. Prinetto:

“System-level modeling and verification: a comprehensive design methodology,”

EDAC'94: The European Conference on Design Automation, Paris (France), February 1994, pp. 636-640

[Con/94-2]

G. Cabodi, P. Camurati, S. Quer:

“Symbolic Traversals of Data Paths with Auxiliary Variables,”

GLS-VLSI'94: 4th IEEE Great Lakes Symposium on VLSI, Notre Dame, IN (USA), March 1994, pp. 93-96

[Con/94-3]

P. Camurati, F. Corno, M. Meo, P. Prinetto:

“A New Functional Fault Model for System-Level Descriptions,”

VTS'94: 12th IEEE VLSI Test Symposium, Cherry Hill, NJ (USA), April 1994 pp. 214-219

[Con/94-4]

P. Camurati, P. Prinetto, M. Sonza Reorda, S. Barbagallo, A. Burri, D. Medina:

“An industrial experience in the built-in self test of embedded RAMs,”

VTS'94: 12th IEEE VLSI Test Symposium, Cherry Hill, NJ (USA), April 1994 pp. 306-311

[Con/94-5]

G. Cabodi, P. Camurati, S. Quer:

“Detecting hard faults with combined approximate forward / backward symbolic techniques,”

ISCAS'94: IEEE International Symposium on Circuits and Systems, London (United Kingdom), May 1994, pp. 299-302

[Con/94-6]

G. Cabodi, P. Camurati, S. Quer:

“Auxiliary variables for extending symbolic traversal techniques to data paths,”

DAC-31: 31st ACM/IEEE Design Automation Conference, San Diego, CA (USA), June 1994, pp. 289-293

[Con/94-7]

G. Cabodi, P. Camurati, S. Quer:

“Symbolic Exploration of Large Circuits with Enhanced Forward/Backward Traversals,”

IEEE EURO-DAC94, Grenoble (France), September 1994, pp. 22-27 (Best Paper Award)

[Con/94-8]

G. Cabodi, P. Camurati, S. Quer:

“Full Symbolic ATPG for Large Circuits,”

ITC'94: IEEE International Test Conference, Washington, DC (USA), October 1994, pp. 980-988

[Con/94-9]

G. Cabodi, P. Camurati, S. Quer:

“Efficient State Space Pruning in Symbolic Backward Traversal,”

ICCD'94: IEEE International Conference on Computer Design, Cambridge, MA (USA), October 1994, pp. 230-235

1995

[Con/95-1]

G. Cabodi, P. Camurati, S. Quer:

“Computing subsets of equivalence classes for large FSMs,”

IEEE EURO-DAC'95, Brighton (UK), September 1995, pp. 288-293

[Con/95-2]

G. Cabodi, P. Camurati, S. Quer:

“Extending Equivalence Class Computation to Large FSMs,”

ICCD'95: IEEE International Conference on Computer Design, Austin, TX (USA), October 1995, pp. 258-263

[Con/95-3]

G. Cabodi, P. Camurati, S. Quer:

“Transforming Boolean Relations by Symbolic Encoding,”

CHARME'95: IFIP WG10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Frankfurt (Germany), October 1995, Lecture Notes in Computer Science n. 987, Springer Verlag, pp. 161-170

1996

[Con/96-1]

G. Cabodi, P. Camurati, S. Quer:

“Decomposed Symbolic Forward Traversals of Large Finite State Machines,”

IEEE EURO-DAC'96, Geneva (Switzerland), September 1996, pp. 170-175

[Con/96-2]

S. Quer, G. Cabodi, P. Camurati, L. Lavagno, E.M. Sentovich, R.K. Brayton:

“Incremental Re-encoding for Symbolic Traversal of Product Machines,”

IEEE EURO-DAC'96, Geneva (Switzerland), September 1996, pp. 158-163

[Con/96-3]

G. Cabodi, P. Camurati, L. Lavagno, E. Macii, M. Poncino, S. Quer, E.M. Sentovich:

“Enhancing FSM Traversal by Traversal Re-Encoding,”

ICCD'96: IEEE International Conference on Computer Design, Austin, TX (USA), October 1996, pp. 6-11

[Con/96-4]

G. Cabodi, P. Camurati, S. Quer:

“Verification and Synthesis of Counters based on Symbolic Techniques,”

SMACD'96: 4th International Workshop on Symbolic Methods and Applications in

Circuit Design, Heverlee (Belgium), October 1996

[Con/96-5]

G. Cabodi, P. Camurati, S. Quer:

“Improved Reachability Analysis of Large Finite State Machines,”

ICCAD'96: IEEE International Conference on Computer Aided Design, San Jose, CA (USA), November 1996, pp. 354-360

1997

[Con/97-1]

G. Cabodi, P. Camurati, S. Quer:

“Verification and Synthesis of Counters based on Symbolic Techniques,”

IEEE ED&TC, Paris, March 1997, pp. 176-181

[Con/97-2]

G. Cabodi, P. Camurati, L. Lavagno, S. Quer:

“Disjunction Partitioning and Partial Iterative Squaring: an effective approach for symbolic traversal of large circuits,”

DAC-34: 34th ACM/IEEE Design Automation Conference, Anaheim, CA (USA), June 1997, pp. 728-733

[Con/97-3]

G. Cabodi, P. Camurati, A. Lioy, M. Poncino, S. Quer:

“A Parallel Approach to Symbolic Traversal based on Set Partitioning,”

CHARME'97: IFIP WG10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods, Montréal, Canada, October 1997, Chapman & Hall, pp. 167-184

1998

[Con/98-1]

G. Cabodi, P. Camurati, S. Quer:

“Reducing Operation Complexity in Symbolic Techniques through Partitioning,”

ISCAS'98: IEEE International Symposium on Circuits and Systems, Monterrey, CA (USA), June 1998, pp. 728-733

[Con/98-2]

G. Cabodi, P. Camurati, L. Lavagno, S. Quer:

“Using Timed Transition Relations in sequential cycle-based simulation”

IWLS'98: IEEE/ACM International Workshop on Logic Synthesis, Lake Tahoe, California, June 1998, no proceedings available

1999

[Con/99-1]

G. Cabodi, P. Camurati, C. Passerone, S. Quer:

“Computing Timed Transition Relations for sequential cycle-based simulation”

DATE'99: IEEE Design Automation and Test in Europe, Munich, Germany, March 1999, pp. 8-12

[Con/99-2]

G. Cabodi, P. Camurati, S. Quer:

“Improving Symbolic Traversals by means of Activity Profiles”

DAC-36: 36th ACM/IEEE Design Automation Conference, New Orleans, Louisiana, June 1999, pp. 306-311

2000

[Con/00-1]

G. Cabodi, P. Camurati, S. Quer:

“Optimizing Sequential Verification by Retiming Transformations,”

DAC-37: 37th ACM/IEEE Design Automation Conference, Loa Angeles, CA, June 2000, pp. 601-606

2001

[Con/01-1]

G. Cabodi, P. Camurati, S. Quer:

“Biasing Symbolic Search by means of Dynamic Activity Profiles”

DATE'01: IEEE Design Automation and Test in Europe, Munich, Germany, March 2001, pp.

2002

[Con/02-1]

G. Cabodi, P. Camurati, S. Quer:

“Dynamic scheduling and clustering in symbolic image computation”

DATE'02: IEEE Design Automation and Test in Europe, Paris, France, March 2002, pp. 150-156

[Con/02-2]

G. Cabodi, P. Camurati, S. Quer:

``Can BDDs compete with SAT solvers on Bounded Model Checking?’’

DAC'39: 39st ACM/IEEE Design Automation Conference, New Orleans, Louisiana, June 2002, pp. 117-122