IT
EN
FR
عربي
Information
Course Catalogue
Services for businesses
Training Projects
Search
Menu secondario
Appointed teaching professor
Syllabus
Concept map
Didactic plan
Exam Guide
Agenda
Learning Environment
Videolessons
Slides
Books and Articles
CD-ROM
Bibliography
Siteography
Laboratory
Exercises
Past interactive classes
Done Virtual Classrooms
Programme Schedule
Tutor
Engineering Area
Computer Architecture
Slides
Lesson n. 1:
The Role of Performance – Part 1
Course objectives - Hardware and Software interface
References
Lesson Summary
The first computers
Internal structure
Computers technology and speed
Electronic technology development
Mahafzah Basel
Lesson n. 2:
The Role of Performance – Part 1
Performance
Computers
Models and complex systems
Abstraction levels
Design methodology
The RTL level
Mahafzah Basel
Lesson n. 3:
The Role of Performance – Part 3
Combinatory and sequential modules
Operations on words
The multiplexer
The decoder
Logic matrixes
Computational Elements
HW description languages
Memory elements
Mahafzah Basel
Lesson n. 4:
Instructions: Language of the Machine – Part 1
Counters
Interconnections
Bus
RTL level structure
RTL language
Mahafzah Basel
Lesson n. 5:
Instructions, Language of the Machine, Part 2
Execution-control unit
Data path
cabled control
Microprogramming
Mahafzah Basel
Lesson n. 6:
Arithmetic for Computers – Part 1
Microprogrammed architecture
Control unit
Design phases
Mahafzah Basel
Lesson n. 7:
Arithmetic for Computers - Part 2
Binary multiplier
RTL program
Control signals
Computer system architecture
Mahafzah Basel
Lesson n. 8:
Arithmetic for Computers – Part 3
Architecture of a CPU
Interrupts
CPU - Memory
CPU RTL scheme
Mahafzah Basel
Lesson n. 9:
Arithmetic for Computers – Part 4
CPU
Instruction execution
Control architecture
Machine language
Mahafzah Basel
Lesson n. 10:
The Processor: MIPS Datapath – Part 1
Immediate addressing mode
Direct addressing mode
Indirect addressing mode
Registers
Address types
Extended architecture
Subprograms
Mahafzah Basel
Lesson n. 11:
The Processor: MIPS Datapath – Part 2
Interrupts
Memory
Memories technology
Access time
Mahafzah Basel
Lesson n. 12:
The Processor: MIPS Datapath – Part 3
The system memory
Memories hierarchy
Locality
Management criteria
The virtual memory
Mahafzah Basel
Lesson n. 13:
The Processor: MIPS Control – Part 1
Substitution policies
Cache memory
Specific problems
Mahafzah Basel
Lesson n. 14:
The Processor: MIPS Control – Part 2
Course contents
Lesson contents
A little bit of history
Programming models
Memory structure and segmentation
Mahafzah Basel
Lesson n. 15:
The Processor: MIPS Control – Part 3
Comments on the x86 architecture
The BUS
The instructions queue
The instruction set
Mahafzah Basel
Lesson n. 16:
The Processor: Single-Cycle Implementation
The instruction format
Addressing
Model evolution
Mahafzah Basel
Lesson n. 17:
Enhancing Performance with Pipelining
Assembler language
Syntax
Execution
DOS functions
Mahafzah Basel
Lesson n. 18:
A Pipelined Datapath – Part 1
DOS calls
Subprograms and modules
Translation
Mahafzah Basel
Lesson n. 19:
A Pipelined Datapath – Part 2
Input / Output interfaces
Program control management
Mahafzah Basel
Lesson n. 20:
A Pipelined Control Unit
Interrupt control management
Interrupt system
Interrupt driver
Mahafzah Basel
Lesson n. 21:
Large & Fast: Exploring Memory Hierarchy – Part 1
Multiple interrupts management system
Vectorization
DMA
Mahafzah Basel
Lesson n. 22:
Large & Fast: Exploring Memory Hierarchy – Part 2
System bus
Protocols
BUS PCI
Mahafzah Basel
Lesson n. 23:
Large & Fast: Exploring Memory Hierarchy – Part 3
CISC and RISC architecture
Performances
Mahafzah Basel
Lesson n. 24:
Large & Fast: Exploring Memory Hierarchy – Part 4
The model
Pipeline levels
Mahafzah Basel
Lesson n. 25:
Large & Fast: Exploring Memory Hierarchy – Part 5
Unordered execution
Examples
Mahafzah Basel